1. Technical Field
The present invention relates to a semiconductor device including a capacitor with a metal-insulator-metal (MIM) structure.
2. Related Art
Recently, an MIM capacitor, in which a parasitic resistance and parasitic capacitance are remarkably small in comparison with a conventional metal oxide semiconductor (MOS) capacitor, has been used more often for a capacitor element. Moreover, a one-chip structure in which such MIM capacitors are built into a logic device has been developed, too. In order to achieve the above structure, the structures and the manufacturing processes for both of the logic device and the capacitor device have been required to be integrated. A common logic device includes a multilayer structure in which interconnections are stacked to form a multi-layered structure. It is an important technical project to apply the structure and the process for the MIM capacitor to the above multi-layered interconnection structure. Considering the above circumstances, a process, according to which an electrode of the MIM capacitor is manufactured in a similar technique to that of the multilayer interconnection structure in a device region, has been developed.
U.S. Laid-open patent application publication No. 2002/0047154 has disclosed a multilayer capacitor-structure in which a first level layer, a second layer, and an insulating film are included, wherein conductive lines are arranged in parallel to one another in the first level layer, conductive lines provided facing the conductive lines in the first level layer are arranged in parallel to one another in the second level layer, and the insulating film formed between the first and second layers.
However, when there are variations in an interconnection pattern at forming the multilayer interconnection structure, there is caused a problem that a flattened layer is not realized, and the dimensional accuracy is deteriorated. In order to solve the above problem, there is used a technique according to which the uniformity of the interconnection density of an interconnection layer is improved by arranging a dummy interconnection in an interconnection layer related with a circuit function of an integrated circuit formed in a semiconductor device. Japanese Laid-open patent publication NO. 2001-196372 has disclosed a technique according to which the above dummy interconnection is not set to be electrically floating, but is fixed at the ground potential.
Incidentally, a capacitor element has had a problem that the finer semiconductor device causes other interconnections formed in a surrounding region of the capacitor to have the influence on the device, and a capacitance value of the capacitor to become unstable. Japanese Laid-open patent publication NO. H5-90489 has disclosed a configuration in which, in a semiconductor integrated circuit provided with a capacitor element in which a lower electrode is formed on a semiconductor substrate, and an upper electrode with a polygonal shape is formed thereabove, shields formed of the same material as that of the upper electrode are arranged, respectively, at positions which are opposed to and apart from each side of the polygonal upper electrode. Thereby, a capacitor with high resistance to disturbances, small additional capacitance, and high accuracy is formed even under the finer structure, according to Japanese Laid-open patent publication NO. H5-90489.
However, the configuration of the semiconductor integrated circuit described in Japanese Laid-open patent publication NO. H5-90489 has a problem that a shielding effect against a leakage electric field to the lower electrode is small, as the shields are arranged, respectively, at positions which are opposed to and apart from each side of the polygonal upper electrode. Moreover, there is also a problem that dimensional accuracy at forming the lower electrode may not be improved.